The present invention relates to phase-locked loop circuitry, and more specifically to a phase-and-frequency mode/phase mode detector with the same gain in both modes.
Phase-locked loop (PLL) circuits are widely used in electronic systems for clock recovery, frequency synthesis, and many other applications. PLL circuits are discussed in the following references:
1. "Phaselock Techniques", by Floyd M. Gardner, John Wiley & Sons, 1979.
2. Phase-locked Loops-Theory, Design, and Applications, by Dr. Roland E. Best, McGraw-Hill, 1984.
These references are hereby incorporated by reference.
A phase detector is usually required to compare the phase difference between a PLL clock signal and a reference signal. The requirements of a phase detector are determined by its application. For example, in a PLL circuit for frequency synthesis, the phase detector must also be able to detect frequency differences before measuring phase differences. However, in other applications, a phase-only detector may be required if the input reference signal is not a periodic waveform.
For example, for clock recovery in the read channel of a disk drive, a PLL circuit must lock to a crystal clock source during the initial power-up period or during the period in which the drive is not reading data from the disk. Since it is possible to have the PLL circuit driven out of frequency lock by a write-splice, it is important for the PLL circuit to be able to detect both phase and frequency difference during those periods. When the disk drive starts reading data, the PLL circuit has to remain locked at the crystal clock frequency. If the industry standard Modified Frequency Modulation (MFM) encoding scheme is employed, the frequency of the data may vary by a factor of two. Since the rising edge of the data pulse is located at the center of a bit cell and the rising edge of the clock pulses are located at the beginning of a bit cell, the frequency of the PLL clock signal must be twice the data rate. Thus, to avoid locking to the sub-harmonics of the crystal frequency, a phase-only detector must be used when the drive is reading data from the disk.
A common solution to the problem is to switch between two phase detectors in the PLL circuit: a phase-only detector and a phase-and-frequency detector. However, it is difficult to design a PLL circuit with two phase detectors, since the gains of the detectors may not be the same. Consequently, a complicated circuit may be required to compensate for the difference in detector gains.
Therefore, it would be desirable to produce a phase detector which may be used for both phase-only and phase-and-frequency operation and whose gain does not change when switched from one mode to the other.